Typically in a general image sensor, electrical charge stored in a light receiving unit such as a photodiode is read as a signal, and then, analog/digital (A/D) conversion is performed for such a signal (see, e.g., Patent Document 1).
Such A/D conversion has been generally performed in such a manner that a signal read from a pixel having a light receiving unit is compared with a reference voltage such as a ramp wave and a time until such a comparison result changes is measured. In recent years, gradation enhancement in this A/D conversion has been demanded for image quality enhancement. Note that high-speed performance in processing and suppression of an increase in circuit dimensions and power consumption have been additionally demanded. For these reasons, Patent Document 1 describes a method in which two types of reference voltages with different gradients are prepared, a determination unit configured to determine the level of a pixel output signal is additionally provided, and either one of the two reference voltages is selected according to such a determination result such that the selected reference voltage is used for comparison with a signal read from a pixel.
Meanwhile, circuit miniaturization has been recently advanced for, e.g., size reduction and power consumption reduction. With circuit miniaturization, e.g., a distance between signal wirings is shortened, and this might lead to occurrence of a parasitic capacitance. For example, a case is conceivable, in which a control circuit for selecting a reference voltage is formed near an input terminal of a comparison unit configured to compare a signal read from a pixel with the reference voltage and a parasitic capacitance is caused between a wiring in the control circuit and the input terminal. In this case, the input terminal of the comparison unit as a series-capacitance floating node might be subjected to coupling due to signal transition of the wiring in the control circuit.
For example, in the case of performing correlated double sampling in A/D conversion, the signal level of a signal transmitted via the wiring in the control circuit might be different between a reset period and a signal reading period in correlated double sampling, and a fluctuation amount of a coupling voltage on the input terminal of the comparison unit in the reset period might be different from that in the signal reading period. With such a difference in the coupling voltage fluctuation amount between the reset period and the signal reading period, an error is caused in a correlated double sampling result due to the fluctuation amount difference, and as a result, there is a probability that A/D conversion cannot be accurately performed.
For reducing such an error, the parasitic capacitance may be reduced by a shield wiring provided with a fixed potential or a sufficient distance between wirings.